1. Field of the Invention
The present invention relates to compatibility considerations in computer systems, and more particularly to auxiliary address decodes which provide faster response times for addressing control signals to meet address decode delay requirements.
2. Description of the Prior Art
The personal computer industry is a vibrant and growing field that continues to evolve as new innovations occur. The driving force behind this innovation has been the increasing demand for faster and more powerful personal computers. Another major factor in the success of the personal computer industry has been the concern on the part of system designers to maintain compatibility between the newer systems that are being developed and the older systems that are currently on the market or in use.
In 1981, International Business Machines Corp. (IBM) introduced its personal computer, the IBM PC. The IBM PC utilized an Intel Corporation (Intel) 8088 as the microprocessor. The 8088 included 20 address pins, which meant that it could directly address 1 Mbyte of memory. The bus architecture in the IBM PC utilized 20 address lines which were referred to as the system address lines SA&lt;19-0&gt;. The SA&lt;19-0&gt; address lines utilized a timing standard that was designed for the relatively slow memory devices available at that time and the timing of the signals produced by the 8088.
Soon after the introduction of the IBM PC, however, 1 Mbyte of memory was no longer sufficient to meet the increasing consumer demand for computer memory, and it became necessary to increase the amount of memory addressability to enable larger amounts of memory to be used in the computer. Therefore, Intel introduced the 80286 microprocessor which included 24 address lines, enabling it to directly address 16 Mbytes of memory. To take advantage of the increased addressing capability of the 80286, it became necessary to extend the address bus of the IBM PC to 24 address lines.
During this period from the introduction of the 8088 microprocessor to the introduction of the 80286 microprocessor, memory component capabilities and speeds increased dramatically, resulting in faster memory access times. The original SA&lt;19-0&gt; address lines used in the IBM PC incorporated a timing standard that was too slow to take advantage of these advances in memory speeds. Therefore, an extended version of the bus architecture used in the IBM PC was introduced in a new personal computer from IBM called the PC/AT. The bus architecture in the PC/AT included a new set of address lines, the latched address lines LA&lt;23-17&gt;, which incorporated a timing standard that took advantage of these faster memory devices. The bus interface standard used in the IBM PC/AT has generally become known as the industry standard architecture (ISA).
As is inevitable in the computer and electronics industry, capabilities of the various components, including memory components, continued to increase. In conjunction with these developments, Intel introduced the 80386 microprocessor. The 80386 microprocessor has an increased speed of operation over the 80286 and includes 32 address lines, allowing for up to 4 Gbytes of direct addressability. In order to take full advantage of the full capabilities of the 80386 microprocessor, an extended version of the ISA was developed called the extended industry standard architecture (EISA). EISA includes a 32-bit address bus, a 32-bit data bus, and full backwards compatability with all ISA devices and software.
The MS-DOS operating system was developed by Microsoft Corp. and IBM as the operating sytem used by the IBM PC and PC/AT. To the operating system and the ISA, the first 640 kbytes of memory is available for use by the operating system and user programs. Portions of the remaining 384 kbytes were reserved for use by the BIOS read only memories (ROM's) of the computer, video memory and peripheral interface boards. Generally the peripheral I/O cards or modules are allocated a 128 kbyte block of memory located from memory address 000C 0000h to 000D FFFFh. The various boards use portions of this memory as necessary. Exemplary boards include network interface boards, optional video boards, and so on.
A standard feature of computers based on the ISA is that certain ISA control signals are decoded from the memory address space and are used to facilitate memory accesses. One such signal that is generally decoded from a memory address for external cards is the M16* signal, which, when asserted low, indicates to the system that the addressed memory is capable of transferring 16 bits of data at once.
Because the M16* signal was available only in systems having the latched address lines LA&lt;23-17&gt;, it was presumed that 16 bit devices would use those signals for their address decode, thus allowing the M16* signal to be developed at a given time in a cycle.
However, some board designers still developed the address decode from SA&lt;19-0&gt; signals but drove the M16* signal to indicate 16 bit transfers. This has created a problem in some computer systems because the M16* signal thus develops too late in the cycle and is not recognized, thus resulting in a performance decrease because 8 bit cycles are then performed.